1. Field of the Invention
This invention relates to computer memory systems, and more particularly to the manufacture of semiconductor memory devices.
2. Description of the Related Art
Personal computers, workstations, and graphics subsystems include memory systems for storing data. An ever increasing demand exists for larger and faster memory systems. Attributes of memory technologies include data access time (i.e., "speed"), cost, reliability, size (i.e., density), and electrical power dissipation. Semiconductor dynamic random access memory (DRAM) represents an acceptable compromise for many applications, and is commonly used in memory systems.
The basic unit of DRAM is the memory cell. Several different types of DRAM cells exist, each having a number of transistors arranged in different configurations. The most popular DRAM cell is the one-transistor cell which allows the highest density. FIG. 1 is a circuit diagram of a typical one-transistor DRAM cell 10. DRAM cell 10 includes a metal oxide semiconductor (MOS) "transfer" transistor 12 coupled to a charge storage capacitor 14. DRAM cell 10 stores a binary digit (i.e., bit) of data as a quantity of electrical charge upon capacitor 14.
Transistor 12 has a drain terminal connected to a "bit" line 16, a gate terminal connected to a "word" line 18, and a source terminal connected to one of two terminal of capacitor 14. The other terminal of capacitor 14 is connected to a "plate" conductor 20. Plate conductor 20 is connected to a fixed electrical potential (e.g., an electrical ground potential V.sub.SS, an electrical power supply voltage V.sub.DD, etc.). Transistor 12 ac a switch, allowing a transfer or "flow" of charge carriers (i.e.., electrons) between capacitor 14 and bit line 16 when activated via a voltage driven upon word line 18. In order to "read" the data stored within DRAM cell 10, a sense amplifier (i.e., sense amp) connected to the bit line is typically used to detect voltage fluctuations on the bit line as a result of a transfer of charge between capacitor 14 and bit line 16.
In DRAM cell 10, a relatively large amount of electrical charge stored upon capacitor 14 represents a stored logic "1", and a relatively small amount of charge stored upon capacitor 14 represents a stored logic "0". The charge stored upon capacitor 14 decays with time due to various "leakage" currents (e.g., through transistor 12: gate structure, source/drain parasitic junctions, and isolation structures). The amount of time capacitor 14 retains a quantity of charge required to distinguish a logic "1" from a logic "0" typically ranges from tens of milliseconds to hundreds of milliseconds. A periodic "refresh" is therefore necessary to restore the charge stored upon capacitor 14.
A photolithographic process is typically used to form DRAM cell elements upon an upper surface of a semiconductor substrate. Continuing advances in photolithographic processes have allowed a reduction in the physical dimensions of DRAM cell elements in two dimensions (i.e., an X-Y plane of the upper surface of the semiconductor substrate). Several factors influence the required charge storing capacity (i.e., the capacitance) of capacitor 14, including the sensitivity of the sense amp, data retention time, and the ability to retain data despite "single-event upsets" due to alpha particles and cosmic rays. Due to these factors, the required capacitance of capacitor 14 has remained relatively constant. As the capacitance of a particular capacitor structure is directly dependent upon the volume the capacitor occupies, the volume of capacitor 14 has remained relatively constant despite X-Y dimension reduction capability afforded by photolithographic advances.
The desire to increase DRAM cell density has led many to form capacitor 14 above or below the surface of the semiconductor substrate (i.e., in the Z dimension normal to the surface, forming three-dimensional or "3-D" DRAM cells). Such 3-D DRAM cells typically include "trench" capacitors formed under the surface of the semiconductor substrate, or "stacked" capacitors formed above the surface of the substrate.
FIG. 2 is a cross-sectional view of a typical trench capacitor DRAM cell 30. In order to form the DRAM cell capacitor, material is removed from a region near an upper surface of substrate 32, forming a trench. Substrate 32 is predominantly semiconductor material heavily doped with an n-type impurity (i.e., n+), and has an upper epitaxial layer of p-type material. The trench extends through the p-type epitaxial layer and into the n+ bulk. The trench is lined with a dielectric layer 34, then filled with an electrically conductive fill material 36 (e.g., n+ polycrystalline silicon, or n+ poly-Si). A relatively thick insulating collar 38 may be formed along a sidewall of the trench.
The transfer transistor of DRAM cell 30 is an MOS transistor including a n+ drain region 40 and a n+ source region 42 formed within the p-type epitaxial layer. A dielectric layer 46 separates an electrically conductive word line 48 from drain region 40 and source region 42. The portion of word line 48 passing over drain region 40 and source region 42 functions as a gate electrode of the transfer MOS transistor. A bit line 50 extends downward through a dielectric layer 52 to make contact with n+ drain region 40. A shallow trench isolation (STI) region 54 may be formed around an upper potion of the trench.
The electrically conductive fill material 36 within the trench makes electrical contact with n+source region 42, and forms one "plate" of the capacitor of DRAM cell 30. The other plate of DRAM cell capacitor 30 is the underlying n+ bulk of substrate 32. The n+ bulk of substrate 32 is connected to a fixed electrical potential (e.g., V.sub.DD or V.sub.SS). Dielectric layer 34 separates the two plates of DRAM cell capacitor 30.
FIG. 3 is a cross-sectional view of a typical capacitor over bit line (COB) stacked capacitor DRAM cell 60. In DRAM cell 60, the capacitor is formed above the surface of a p-type substrate 62, and above a bit line 64. The transfer transistor of DRAM cell 60 is an MOS transistor including an n+ drain region 66 and an n+ source region 68 formed within p-type substrate 62. A dielectric layer 70 separates an electrically conductive word line 72 from drain region 66 and source region 68. The portion of word line 72 passing over drain region 66 and source region 68 functions as a gate electrode of the transfer MOS transistor. Bit line 64 extends downward through a dielectric layer 74 to make contact with n+ drain region 66.
An electrically conductive block 76 formed above bit line 64 is connected to n+ source region 68 by an electrically conductive pillar 78. Block 76 may be formed from, for example, n+ poly-Si. Pillar 78 electrically connects block 76 to n+ source region 68, and extends through a dielectric layer 80, between bit line 64 and block 76, and dielectric layer 74 between bit line 64 and word line 72. A dielectric layer 82 is formed over block 76, and an electrically conductive plate conductor 84 is formed over dielectric layer 82. Block 76 is one plate of the capacitor of DRAM cell 60, and makes electrical contact with n+ source region 68. The other plate of the DRAM cell capacitor is plate conductor 84.
FIG. 4 is a top plane view of a portion of a typical layout of a two-dimensional array of trench capacitor DRAM cells 90 within a memory device. Bit lines labeled "bm" define vertical columns of the array, when m is an integer index. Word lines labeled "wxn" define horizontal rows of the array, when n is an integer index. Capacitors of the array are represented by oblong squares and labeled "cnm", where each capacitor is associated with word line "wxn" and a bit line "bm". Portions of word lines "wxn" functioning as gate electrodes of transfer transistors are represented by the symbol "x". Electrical contacts extending downward from the bit lines to the drain regions of the transfer transistors are represented by small ovals along the bit lines. DRAM cells 90 are arranged in adjoining pairs aligned along the bit line columns, and share common bit line electrical contacts.
The cost of manufacturing a semiconductor memory device is directly proportional to the size of the substrate (i.e., die). It would thus be desirable to have a memory device including a larger number of DRAM cells per unit of substrate surface area (i.e., having an increased DRAM cell density). Such an increase in cell density would allow more data storage per unit of substrate surface area, reducing the manufacturing cost of the memory device per bit of data storage.